1. Field of the Invention
This invention relates to digital communications and more specifically to an equalizing and data recovery method and apparatus for eliminating in a receiver frequency domain distortion introduced by a transmission channel.
2. Description of the Prior Art
As is well known in the digital communications (e.g. computer data transmission) field, a basic problem is frequency domain distortion and noise introduced by the transmission channel. A transmission channel is for instance a telephone line, microwave relay, coaxial cable or satellite link. At the receiver end of the transmission channel, the received analog signal is equalized and the digital data recovered. Equalization is the well known process of removing distortion in the frequency domain, thereby overcoming the distorting affects of the transmission channel. Data recovery is the process of extracting a digital signal from the equalized analog signal. Typically for a single transmission channel system, a synchronizing clock signal is first recovered from the received signal prior to recovering the data signal.
Most transmission channel types cause complex frequency domain distortion such that it is difficult and expensive to implement an exact inverse thereof for equalization. Hence, the usual approach, which is to settle for less than optimum equalization, renders both clock and data recovery more difficult and lowers the tolerance of the system to noise, thus increasing the bit error rate (BER).
One approach in the prior art is an equalizer that is as close as possible to the transmission channel inverse. Such an apparatus reverses the frequency domain distortions imposed by the channel and also makes the data recovery circuit as tolerant as possible to whatever flaws are present in the equalizer. This solution has been found generally to be inferior because it increases the difficulty and therefore the expense of implementing both the equalizer and the data recovery circuits.
FIG. 1 shows a feedback equalizer apparatus 10 which is the receiver end of a digital transmission system. A transmitter 12 which receives e.g. computer data for transmission along for instance a coaxial cable transmission channel 16 transmits digital data along the transmission channel 16 to receiver 10. The receiver 10 includes a number of elements. The received signal is first subject to an analog equalization by equalizer 18 which is a rough attempt to reverse the effects of the distortion, in the frequency domain, introduced by the transmission channel.
In order to minimize the cost of the equalizer 18, the equalizer 18 performs only an approximation of an inverse of the effects of the channel 16. The output signal from the equalizer 18, which is an analog signal, is then applied to the input terminal of a slicer 22 which is a decision-making element. The slicer 22 receives the signal output from the equalizer 18 and outputs a signal, e.g. on a two-level bus. The equalizer is typically an analog high pass filter and the slicer is an analog circuit which merely decides in which range (of possibly many, e.g. three) the analog signal falls and outputs a value to indicate the range.
The signal output from the slicer 22 is provided to a clock and data recovery circuit 26 which independently recovers the synchronizing clock signals and the digital data signals from the sliced signal. The data recovery is accomplished by sampling the sliced signal at a fixed clock rate determined by the recovered clock signal. In addition, a feedback filter element 28 is present whereby the output signal from the slicer 22 is subject to a digital linear filter 28 and summed back by summer 32 to the signal output by the equalizer 18. This process is intended to improve the quality of the equalization. However this process suffers from the need to know the gain of the equalizer 18, any distortion introduced by the summer 32, and also by any limitations in the filter 28. This process also does not include the actual clock and data recovery circuit 26 in the feedback loop and hence it is unable to correct problems in clock data recovery and has been found to be inadequate. Also the filter 28 by its nature requires special filter coefficients which are difficult to implement in typical digital circuitry. Also this technique requires minimum time delay through the feedback equalizer, which however is difficult to achieve. Hence this implementation is relatively complex.
Also, the present inventors have determined that the prior art approach suffers from the drawback shown in FIG. 2 where the slicer threshold values are fixed. FIG. 2 shows a waveform where the vertical axis is amplitude (voltage) and the horizontal axis is time, as applied to slicer 22 in FIG. 1. There are two slicer thresholds P (positive) and N (negative); pulse X is a negative pulse of low amplitude and above the threshold N (e.g. due to signal drift caused by long pulse Y and an equalizer that is not the exact inverse of the cable) and hence undesirably is missed (not detected) by the slicer.
Therefore there are no known means in the prior art to accomplish accurate equalization and data recovery (providing a signal with a low number of error bits) in a relatively economical implementation.